Verilog Vivado Count_8 Bit.v Code

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`timescale 1ns / 1ps
// 8 bit counter
// input : rst, clk
// output, cntout [7:0]
module count_8bit(
    input rst,
    input clk,
    output [7:0] cntout
    );
    reg [7:0] out;
    
    always @ (posedge clk or posedge rst ) begin
        if(rst == 1'b1) begin
            out <= 8'b0000_0000;
        end
        
        else begin
            out <= out + 1'b1;
        end
    end
    assign cntout = out;
endmodule

This is the Verilog code that written with Vivado for implementing Stopwatch in FPGA Board(Xilinx; Nexys S).

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Verilog Vivado Lab14Stopwatch.v Code

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////

module Lab14stopwatch(
    input en,
    input clk,
    input rst,
    output [7:0] AN,
    output secled,
    output [7:0] Seg
    );
    wire [3:0] X0, X1, X2, X3;
    
    stopwatch u0 (.rst(rst), .en(en), .clk(clk), .secled(secled), .Q10(X0), .Q1(X1), .Qs1(X2), .Qs10(X3));
    Dsp7Seg u1(.X0(X0), .X1(X1), .X2(X2), .X3(X3), .rst(rst), .clk(clk), .dsp(Seg), .AN(AN));
endmodule

This is the Verilog Code that written with Vivado for implementing Stopwatch.

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Verilog tb_FullAdder.v Code  (0) 2019.05.26
Verilog tb_Dsp7Seg.v Code  (0) 2019.05.26

Verilog tb_HalfAdder.v Code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/05/22 16:01:17
// Design Name: 
// Module Name: tb_HA
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_HA(

    );
    reg A, B;
    wire carry, sum;
    HA U0(.A(A), .B(B), .Cout(carry), .S(sum));
    
    initial begin
        A=0; B=0;
        #100 B=1;
        #100 A=1;
        #100 B=0;
        #100 $finish;
    end
    
    
endmodule

test bench simulation source code file for HalfAdder.v (or HA.v)

tb is short term for 'test bench'. All these test bench codes are for running simulation of design sources.

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Verilog tb_Dsp7Seg.v Code  (0) 2019.05.26
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Verilog tb_FullAdder.v Code

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
module tb_FA(
    );
    reg in1,in2,in3;
    wire carry,sum;
    
    FA U1(.A(in1),.B(in2),.Cin(in3),.Cout(carry),.S(sum));
    initial begin
        in1=0;in2=0;in3=0;      //000 -> 00
        #100 in3=1;             //001 -> 01
        #100 in2=1;             //011 -> 10
        #100 in1=1;             //111 -> 11
        #100 in3=0;             //110 -> 10
        #100 in2=0;             //100 -> 01
        #100 $finish;
    end
endmodule

test bench simulation source code file for FA.v (or FullAdder.v)

tb is short term for 'test bench'. All these test bench codes are for running simulation of design sources.

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Verilog tb_Dsp7Seg.v Code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////
module tb_Dsp7Seg(
    );
    reg [3:0] A,B,C,D,E,F,G,H; // 8-BCD
    reg clk, rst;
    wire [7:0] AN, Seg;
    
    Dsp7Seg U1(.X0(A), .X1(B), .X2(C), .X3(D), .X4(E), .X5(F), .X6(G), .X7(H),
                .clk(clk), .rst(rst),
                .dsp(Seg), .AN(AN));
    initial begin
        A=0;B=1;C=2;D=3;E=4;F=5;G=6;H=7;
        clk=0; rst=1;
        #23 rst=0;
    end
     
    always begin
        #5 clk = !clk;
    end
endmodule

test bench simulation source code file for 'Des7Seg.v'

tb is short term for 'test bench'. All these test bench codes are for running simulation of design sources.

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