Verilog tb_Add4Bit Code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module tb_Add4bit(
    );
    reg [3:0] X,Y;
    wire carry;
    wire [3:0] sum;
    
    Add4bit U0(.A(X),.B(Y),.Cout(carry),.S(sum));
    
    initial begin
        X=4'b000; Y=4'b000; //0+0 = 0.0
        #100 X=4'b1001;     //9+0 = 0. 9
        #100 Y=4'b1010;     //9+a = 1. 3
        #100 $finish;
    end
endmodule

test bench simulation source code file for 'Add4bit.v'

tb is short term for 'test bench'. All these test bench codes are for running simulation of design sources.

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Verilog tb_LabAdd4bit Code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Test for LabAdd4bit :
// A[3:0]=9; B=[3:0]=10 => Carry = 1, Sum = 3
//X0 = h84, X1 = h82, X2 = hCF, X3 = h86
//////////////////////////////////////////////////////////////////////////////////
module tb_LabAdd4bit(
    );
    reg [3:0] A, B;
    reg clk, rst;
    wire [7:0] an, seg;
    
    LabAdd4bit U0(.A(A),.B(B),.clk(clk),.rst(rst),.AN(an),.Seg(seg));
    
    initial begin
        A=4'b1001; B=4'b1010;
        clk=0; rst=1;
        #23 rst=0;
    end
    
    //100MHz clock
    always begin
        #5 clk = !clk;
    end
endmodule

test bench simulation source code file for LabAdd4bit.v

tb is short term for 'test bench'. All these test bench codes are for running simulation of design sources.

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Verilog Lab 4 Bit Adder_xdc Code

# Clock signal
set_property -dict { PACKAGE_PIN E3    IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz

#rst
set_property -dict { PACKAGE_PIN N17   IOSTANDARD LVCMOS33 } [get_ports { rst }]; #IO_L9P_T1_DQS_14 Sch=btnc

#7 segment display
set_property -dict { PACKAGE_PIN T10   IOSTANDARD LVCMOS33 } [get_ports { Seg[6] }]; #IO_L24N_T3_A00_D16_14 Sch=ca
set_property -dict { PACKAGE_PIN R10   IOSTANDARD LVCMOS33 } [get_ports { Seg[5] }]; #IO_25_14 Sch=cb
set_property -dict { PACKAGE_PIN K16   IOSTANDARD LVCMOS33 } [get_ports { Seg[4] }]; #IO_25_15 Sch=cc
set_property -dict { PACKAGE_PIN K13   IOSTANDARD LVCMOS33 } [get_ports { Seg[3] }]; #IO_L17P_T2_A26_15 Sch=cd
set_property -dict { PACKAGE_PIN P15   IOSTANDARD LVCMOS33 } [get_ports { Seg[2] }]; #IO_L13P_T2_MRCC_14 Sch=ce
set_property -dict { PACKAGE_PIN T11   IOSTANDARD LVCMOS33 } [get_ports { Seg[1] }]; #IO_L19P_T3_A10_D26_14 Sch=cf
set_property -dict { PACKAGE_PIN L18   IOSTANDARD LVCMOS33 } [get_ports { Seg[0] }]; #IO_L4P_T0_D04_14 Sch=cg
set_property -dict { PACKAGE_PIN H15   IOSTANDARD LVCMOS33 } [get_ports { Seg[7] }]; #IO_L19N_T3_A21_VREF_15 Sch=dp
set_property -dict { PACKAGE_PIN J17   IOSTANDARD LVCMOS33 } [get_ports { AN[0] }]; #IO_L23P_T3_FOE_B_15 Sch=an[0]
set_property -dict { PACKAGE_PIN J18   IOSTANDARD LVCMOS33 } [get_ports { AN[1] }]; #IO_L23N_T3_FWE_B_15 Sch=an[1]
set_property -dict { PACKAGE_PIN T9    IOSTANDARD LVCMOS33 } [get_ports { AN[2] }]; #IO_L24P_T3_A01_D17_14 Sch=an[2]
set_property -dict { PACKAGE_PIN J14   IOSTANDARD LVCMOS33 } [get_ports { AN[3] }]; #IO_L19P_T3_A22_15 Sch=an[3]
set_property -dict { PACKAGE_PIN P14   IOSTANDARD LVCMOS33 } [get_ports { AN[4] }]; #IO_L8N_T1_D12_14 Sch=an[4]
set_property -dict { PACKAGE_PIN T14   IOSTANDARD LVCMOS33 } [get_ports { AN[5] }]; #IO_L14P_T2_SRCC_14 Sch=an[5]
set_property -dict { PACKAGE_PIN K2    IOSTANDARD LVCMOS33 } [get_ports { AN[6] }]; #IO_L23P_T3_35 Sch=an[6]
set_property -dict { PACKAGE_PIN U13   IOSTANDARD LVCMOS33 } [get_ports { AN[7] }]; #IO_L23N_T3_A02_D18_14 Sch=an[7]

# A value
set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { A[0] }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { A[1] }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN M13   IOSTANDARD LVCMOS33 } [get_ports { A[2] }]; #IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN R15   IOSTANDARD LVCMOS33 } [get_ports { A[3] }]; #IO_L13N_T2_MRCC_14 Sch=sw[3]

# B value
set_property -dict { PACKAGE_PIN R17   IOSTANDARD LVCMOS33 } [get_ports { B[0] }]; #IO_L12N_T1_MRCC_14 Sch=sw[4]
set_property -dict { PACKAGE_PIN T18   IOSTANDARD LVCMOS33 } [get_ports { B[1] }]; #IO_L7N_T1_D10_14 Sch=sw[5]
set_property -dict { PACKAGE_PIN U18   IOSTANDARD LVCMOS33 } [get_ports { B[2] }]; #IO_L17N_T2_A13_D29_14 Sch=sw[6]
set_property -dict { PACKAGE_PIN R13   IOSTANDARD LVCMOS33 } [get_ports { B[3] }]; #IO_L5N_T0_D07_14 Sch=sw[7]

xdc_labadd4bit.xdc , 

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Verilog Half Adder Constraints File

# A, B
set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { A }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { B }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]

# Cout, Sum
set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { S }]; #IO_L18P_T2_A24_15 Sch=led[0]
set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { Cout }]; #IO_L24P_T3_RS1_15 Sch=led[1]

ha_xdc.xdc  , Half Adder Constraints

xdc: Xilinx's Design Constraints File

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Verilog Dsp7Seg.v Code

`timescale 1ns / 1ps

module Dsp7Seg(
    input [3:0] X0,
    input [3:0] X1,
    input [3:0] X2,
    input [3:0] X3,
    input [3:0] X4,
    input [3:0] X5,
    input [3:0] X6,
    input [3:0] X7,
    input clk,
    input rst,
    output reg [7:0] dsp,
    output reg [7:0] AN
    );
    reg [19:0] ref_cnt;
    wire [2:0] act_AN;
    reg [3:0] LED_BCD;
    always @(posedge clk or posedge rst) begin
        if(rst==1)
            ref_cnt <= 0;
        else
            ref_cnt <= ref_cnt +1;
    end
    assign act_AN = ref_cnt[19:17];
    always @(*) begin
        case(act_AN)
        3'b000: begin
            AN = 8'b0111_1111;
            LED_BCD = X0;
        end

        3'b001: begin
            AN = 8'b1011_1111;
            LED_BCD = X1;
        end


        3'b010: begin
            AN = 8'b1101_1111;
            LED_BCD = X2;
        end

        3'b011: begin
            AN=8'b1110_1111;
            LED_BCD = X3;
        end

        3'b100: begin
            AN = 8'b111_0111;
            LED_BCD = X4;
        end 

        3'b101: begin
            AN = 8'b1111_1011;
            LED_BCD = X5;
        end

        3'b110: begin
            AN=8'b1111_1101;
            LED_BCD = X6;
        end

        3'b111:begin
            AN = 8'b1111_1110;
            LED_BCD = X7;
        end
        endcase
    end

    always @(*) begin
        case(LED_BCD)
            4'b0000: dsp = 8'b1000_0001;
            4'b0001: dsp = 8'b1100_1111;
            4'b0010: dsp = 8'b1001_0010;
            4'b0011: dsp = 8'b1000_0110;
            4'b0100: dsp = 8'b1100_1100;
            4'b0101: dsp = 8'b1010_0100;
            4'b0110: dsp = 8'b1010_0000;
            4'b0111: dsp = 8'b1000_1111;
            4'b1000: dsp = 8'b1000_0000; // yet
            4'b1001: dsp = 8'b1000_0100;
            4'b1010: dsp = 8'b1000_0010;
            4'b1011: dsp = 8'b1110_0000;
            4'b1100: dsp = 8'b1111_0010;
            4'b1101: dsp = 8'b1100_0010;
            4'b1110: dsp = 8'b1001_0000;
            4'b1111: dsp = 8'b1011_1000;
        endcase
    end
endmodule

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