Verilog tb_HalfAdder.v Code

Verilog tb_HalfAdder.v Code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/05/22 16:01:17
// Design Name: 
// Module Name: tb_HA
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_HA(

    );
    reg A, B;
    wire carry, sum;
    HA U0(.A(A), .B(B), .Cout(carry), .S(sum));
    
    initial begin
        A=0; B=0;
        #100 B=1;
        #100 A=1;
        #100 B=0;
        #100 $finish;
    end
    
    
endmodule

test bench simulation source code file for HalfAdder.v (or HA.v)

tb is short term for 'test bench'. All these test bench codes are for running simulation of design sources.