Verilog tb_Add4Bit Code

Verilog tb_Add4Bit Code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module tb_Add4bit(
    );
    reg [3:0] X,Y;
    wire carry;
    wire [3:0] sum;
    
    Add4bit U0(.A(X),.B(Y),.Cout(carry),.S(sum));
    
    initial begin
        X=4'b000; Y=4'b000; //0+0 = 0.0
        #100 X=4'b1001;     //9+0 = 0. 9
        #100 Y=4'b1010;     //9+a = 1. 3
        #100 $finish;
    end
endmodule

test bench simulation source code file for 'Add4bit.v'

tb is short term for 'test bench'. All these test bench codes are for running simulation of design sources.