Verilog Vivado Count_8 Bit.v Code
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`timescale 1ns / 1ps
// 8 bit counter
// input : rst, clk
// output, cntout [7:0]
module count_8bit(
input rst,
input clk,
output [7:0] cntout
);
reg [7:0] out;
always @ (posedge clk or posedge rst ) begin
if(rst == 1'b1) begin
out <= 8'b0000_0000;
end
else begin
out <= out + 1'b1;
end
end
assign cntout = out;
endmodule
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This is the Verilog code that written with Vivado for implementing Stopwatch in FPGA Board(Xilinx; Nexys S).