Verilog Vivado Lab14Stopwatch.v Code
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`timescale 1ns / 1ps
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module Lab14stopwatch(
input en,
input clk,
input rst,
output [7:0] AN,
output secled,
output [7:0] Seg
);
wire [3:0] X0, X1, X2, X3;
stopwatch u0 (.rst(rst), .en(en), .clk(clk), .secled(secled), .Q10(X0), .Q1(X1), .Qs1(X2), .Qs10(X3));
Dsp7Seg u1(.X0(X0), .X1(X1), .X2(X2), .X3(X3), .rst(rst), .clk(clk), .dsp(Seg), .AN(AN));
endmodule
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This is the Verilog Code that written with Vivado for implementing Stopwatch.