Verilog tb_Dsp7Seg.v Code

Verilog tb_Dsp7Seg.v Code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
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module tb_Dsp7Seg(
    );
    reg [3:0] A,B,C,D,E,F,G,H; // 8-BCD
    reg clk, rst;
    wire [7:0] AN, Seg;
    
    Dsp7Seg U1(.X0(A), .X1(B), .X2(C), .X3(D), .X4(E), .X5(F), .X6(G), .X7(H),
                .clk(clk), .rst(rst),
                .dsp(Seg), .AN(AN));
    initial begin
        A=0;B=1;C=2;D=3;E=4;F=5;G=6;H=7;
        clk=0; rst=1;
        #23 rst=0;
    end
     
    always begin
        #5 clk = !clk;
    end
endmodule

test bench simulation source code file for 'Des7Seg.v'

tb is short term for 'test bench'. All these test bench codes are for running simulation of design sources.