미래지향적person1

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/05/22 16:01:17
// Design Name: 
// Module Name: tb_HA
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_HA(

    );
    reg A, B;
    wire carry, sum;
    HA U0(.A(A), .B(B), .Cout(carry), .S(sum));
    
    initial begin
        A=0; B=0;
        #100 B=1;
        #100 A=1;
        #100 B=0;
        #100 $finish;
    end
    
    
endmodule

# A, B
set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { A }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { B }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]

# Cout, Sum
set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { S }]; #IO_L18P_T2_A24_15 Sch=led[0]
set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { Cout }]; #IO_L24P_T3_RS1_15 Sch=led[1]

`timescale 1ns / 1ps

module HA(
    input A,
    input B,
    output Cout,
    output S
    );
    assign Cout = A & B;
    assign S = A ^ B;
endmodule

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
module Add4bit(
    input [3:0] A,
    input [3:0] B,
    output Cout,
    output [3:0] S
    );
    wire [2:0] tmp;
    HA U0(.A(A[0]),.B(B[0]),.Cout(tmp[0]),.S(S[0]));
    FA U1(.A(A[1]),.B(B[1]),.Cin(tmp[0]),.Cout(tmp[1]),.S(S[1]));
    FA U2(.A(A[2]),.B(B[2]),.Cin(tmp[1]),.Cout(tmp[2]),.S(S[2]));
    FA U3(.A(A[3]),.B(B[3]),.Cin(tmp[2]),.Cout(Cout),.S(S[3]));
endmodule

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Lab 4bit adder : 

// A[3:0],B[3:0],clk,rst --> AN[7:0], Seg[7:0]

//////////////////////////////////////////////////////////////////////////////////

module LabAdd4bit(
    input [3:0] A,
    input [3:0] B,
    input clk,
    input rst,
    output [7:0] AN,
    output [7:0] Seg
    );
    
    wire [3:0] carry, sum;
    assign carry[3:1] = 3'b000;

    Add4bit U1(.A(A), .B(B), .Cout(carry[0]), .S(sum));
    Dsp7Seg U2(.X0(A), .X1(B), .X2(carry), .X3(sum), .clk(clk), .rst(rst), .AN(AN),.dsp(Seg));
endmodule