Verilog Dsp7Seg.v Code

Verilog Dsp7Seg.v Code

`timescale 1ns / 1ps

module Dsp7Seg(
    input [3:0] X0,
    input [3:0] X1,
    input [3:0] X2,
    input [3:0] X3,
    input [3:0] X4,
    input [3:0] X5,
    input [3:0] X6,
    input [3:0] X7,
    input clk,
    input rst,
    output reg [7:0] dsp,
    output reg [7:0] AN
    );
    reg [19:0] ref_cnt;
    wire [2:0] act_AN;
    reg [3:0] LED_BCD;
    always @(posedge clk or posedge rst) begin
        if(rst==1)
            ref_cnt <= 0;
        else
            ref_cnt <= ref_cnt +1;
    end
    assign act_AN = ref_cnt[19:17];
    always @(*) begin
        case(act_AN)
        3'b000: begin
            AN = 8'b0111_1111;
            LED_BCD = X0;
        end

        3'b001: begin
            AN = 8'b1011_1111;
            LED_BCD = X1;
        end


        3'b010: begin
            AN = 8'b1101_1111;
            LED_BCD = X2;
        end

        3'b011: begin
            AN=8'b1110_1111;
            LED_BCD = X3;
        end

        3'b100: begin
            AN = 8'b111_0111;
            LED_BCD = X4;
        end 

        3'b101: begin
            AN = 8'b1111_1011;
            LED_BCD = X5;
        end

        3'b110: begin
            AN=8'b1111_1101;
            LED_BCD = X6;
        end

        3'b111:begin
            AN = 8'b1111_1110;
            LED_BCD = X7;
        end
        endcase
    end

    always @(*) begin
        case(LED_BCD)
            4'b0000: dsp = 8'b1000_0001;
            4'b0001: dsp = 8'b1100_1111;
            4'b0010: dsp = 8'b1001_0010;
            4'b0011: dsp = 8'b1000_0110;
            4'b0100: dsp = 8'b1100_1100;
            4'b0101: dsp = 8'b1010_0100;
            4'b0110: dsp = 8'b1010_0000;
            4'b0111: dsp = 8'b1000_1111;
            4'b1000: dsp = 8'b1000_0000; // yet
            4'b1001: dsp = 8'b1000_0100;
            4'b1010: dsp = 8'b1000_0010;
            4'b1011: dsp = 8'b1110_0000;
            4'b1100: dsp = 8'b1111_0010;
            4'b1101: dsp = 8'b1100_0010;
            4'b1110: dsp = 8'b1001_0000;
            4'b1111: dsp = 8'b1011_1000;
        endcase
    end
endmodule