Verilog Vivado tb_count_8bit.v Code

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: I am a college student.
// Testbench for count_8bit
//////////////////////////////////////////////////////////////////////////////////
module tb_count_8bit(

    );
    reg clk, rst, en;
    wire [7:0] count, mod_cnt, mod_02;
    wire tc01, tc02;
    
    count_8bit U0(.clk(clk), .rst(rst), .cntout(count));
    
    //Modulus 60: 0,1,2,.... 58, 59, 0, 1, 2, 3,....
    defparam U1.MOD = 10; //0,1,2,....9,0,1,2,3....
    mod_n U1 (.clk(clk), .rst(rst), .en(en), .cntout(mod_cnt), .TC(tc01));

    defparam U1.MOD = 6; //0,1,2,....5,0,1,2,3....
    mod_n U2 (.clk(clk), .rst(rst), .en(tc01), .cntout(mod_02), .TC(tc02));
        
    initial begin
        clk=1'b0;
        rst=1'b0;
        en = 1'b1;
        #1 rst=1'b1;
        #5 rst=1'b0;
        #100 $stop;
    end
    
    //100MHz clock
    always begin
        #5 clk = ~clk;
    end
    
endmodule

This is the Verilog code that written with Vivado for implementing Stopwatch in FPGA Board(Xilinx; Nexys S).

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Verilog tb_HalfAdder.v Code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2019/05/22 16:01:17
// Design Name: 
// Module Name: tb_HA
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_HA(

    );
    reg A, B;
    wire carry, sum;
    HA U0(.A(A), .B(B), .Cout(carry), .S(sum));
    
    initial begin
        A=0; B=0;
        #100 B=1;
        #100 A=1;
        #100 B=0;
        #100 $finish;
    end
    
    
endmodule

test bench simulation source code file for HalfAdder.v (or HA.v)

tb is short term for 'test bench'. All these test bench codes are for running simulation of design sources.

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Verilog tb_FullAdder.v Code

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
module tb_FA(
    );
    reg in1,in2,in3;
    wire carry,sum;
    
    FA U1(.A(in1),.B(in2),.Cin(in3),.Cout(carry),.S(sum));
    initial begin
        in1=0;in2=0;in3=0;      //000 -> 00
        #100 in3=1;             //001 -> 01
        #100 in2=1;             //011 -> 10
        #100 in1=1;             //111 -> 11
        #100 in3=0;             //110 -> 10
        #100 in2=0;             //100 -> 01
        #100 $finish;
    end
endmodule

test bench simulation source code file for FA.v (or FullAdder.v)

tb is short term for 'test bench'. All these test bench codes are for running simulation of design sources.

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Verilog tb_LabAdd4bit Code  (0) 2019.05.26

Verilog tb_Add4Bit Code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module tb_Add4bit(
    );
    reg [3:0] X,Y;
    wire carry;
    wire [3:0] sum;
    
    Add4bit U0(.A(X),.B(Y),.Cout(carry),.S(sum));
    
    initial begin
        X=4'b000; Y=4'b000; //0+0 = 0.0
        #100 X=4'b1001;     //9+0 = 0. 9
        #100 Y=4'b1010;     //9+a = 1. 3
        #100 $finish;
    end
endmodule

test bench simulation source code file for 'Add4bit.v'

tb is short term for 'test bench'. All these test bench codes are for running simulation of design sources.

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Verilog tb_LabAdd4bit Code

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Test for LabAdd4bit :
// A[3:0]=9; B=[3:0]=10 => Carry = 1, Sum = 3
//X0 = h84, X1 = h82, X2 = hCF, X3 = h86
//////////////////////////////////////////////////////////////////////////////////
module tb_LabAdd4bit(
    );
    reg [3:0] A, B;
    reg clk, rst;
    wire [7:0] an, seg;
    
    LabAdd4bit U0(.A(A),.B(B),.clk(clk),.rst(rst),.AN(an),.Seg(seg));
    
    initial begin
        A=4'b1001; B=4'b1010;
        clk=0; rst=1;
        #23 rst=0;
    end
    
    //100MHz clock
    always begin
        #5 clk = !clk;
    end
endmodule

test bench simulation source code file for LabAdd4bit.v

tb is short term for 'test bench'. All these test bench codes are for running simulation of design sources.

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