Verilog Vivado mod_n.v Code
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Modulus N Counter
// Input: rst, clk, en
// Output: cntout[7:0], TC
// parameter : MOD
//////////////////////////////////////////////////////////////////////////////////
module mod_n(
input rst,
input clk,
input en,
output [7:0] cntout,
output reg TC
);
reg [7:0] cnt;
parameter MOD = 5;
always @ (posedge clk or posedge rst) begin
if(rst==1'b1) begin
cnt <= 8'b0000_0000;
TC = 1'b0;
end
else begin
cnt <= (en) ? cnt+1'b1 : cnt;
TC <= 1'b0;
if(en & cnt == MOD-1) begin
cnt <= 8'b0000_0000;
TC <= 1'b1;
end
end
end
assign cntout = cnt;
endmodule
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This is the Verilog code that written with Vivado for implementing Stopwatch in FPGA Board(Xilinx; Nexys S).