미래지향적person1

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
module tb_FA(
    );
    reg in1,in2,in3;
    wire carry,sum;
    
    FA U1(.A(in1),.B(in2),.Cin(in3),.Cout(carry),.S(sum));
    initial begin
        in1=0;in2=0;in3=0;      //000 -> 00
        #100 in3=1;             //001 -> 01
        #100 in2=1;             //011 -> 10
        #100 in1=1;             //111 -> 11
        #100 in3=0;             //110 -> 10
        #100 in2=0;             //100 -> 01
        #100 $finish;
    end
endmodule

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////////////////
module FA(
    input A,
    input B,
    input Cin,
    output Cout,
    output S
    );
    assign {Cout,S} = A+B+Cin;
endmodule

`timescale 1ns / 1ps

module HA(
    input A,
    input B,
    output Cout,
    output S
    );
    assign Cout = A & B;
    assign S = A ^ B;
endmodule

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////
module Add4bit(
    input [3:0] A,
    input [3:0] B,
    output Cout,
    output [3:0] S
    );
    wire [2:0] tmp;
    HA U0(.A(A[0]),.B(B[0]),.Cout(tmp[0]),.S(S[0]));
    FA U1(.A(A[1]),.B(B[1]),.Cin(tmp[0]),.Cout(tmp[1]),.S(S[1]));
    FA U2(.A(A[2]),.B(B[2]),.Cin(tmp[1]),.Cout(tmp[2]),.S(S[2]));
    FA U3(.A(A[3]),.B(B[3]),.Cin(tmp[2]),.Cout(Cout),.S(S[3]));
endmodule

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Lab 4bit adder : 

// A[3:0],B[3:0],clk,rst --> AN[7:0], Seg[7:0]

//////////////////////////////////////////////////////////////////////////////////

module LabAdd4bit(
    input [3:0] A,
    input [3:0] B,
    input clk,
    input rst,
    output [7:0] AN,
    output [7:0] Seg
    );
    
    wire [3:0] carry, sum;
    assign carry[3:1] = 3'b000;

    Add4bit U1(.A(A), .B(B), .Cout(carry[0]), .S(sum));
    Dsp7Seg U2(.X0(A), .X1(B), .X2(carry), .X3(sum), .clk(clk), .rst(rst), .AN(AN),.dsp(Seg));
endmodule