미래지향적person1

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module tb_Add4bit(
    );
    reg [3:0] X,Y;
    wire carry;
    wire [3:0] sum;
    
    Add4bit U0(.A(X),.B(Y),.Cout(carry),.S(sum));
    
    initial begin
        X=4'b000; Y=4'b000; //0+0 = 0.0
        #100 X=4'b1001;     //9+0 = 0. 9
        #100 Y=4'b1010;     //9+a = 1. 3
        #100 $finish;
    end
endmodule

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Test for LabAdd4bit :
// A[3:0]=9; B=[3:0]=10 => Carry = 1, Sum = 3
//X0 = h84, X1 = h82, X2 = hCF, X3 = h86
//////////////////////////////////////////////////////////////////////////////////
module tb_LabAdd4bit(
    );
    reg [3:0] A, B;
    reg clk, rst;
    wire [7:0] an, seg;
    
    LabAdd4bit U0(.A(A),.B(B),.clk(clk),.rst(rst),.AN(an),.Seg(seg));
    
    initial begin
        A=4'b1001; B=4'b1010;
        clk=0; rst=1;
        #23 rst=0;
    end
    
    //100MHz clock
    always begin
        #5 clk = !clk;
    end
endmodule

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////////////////
module FA(
    input A,
    input B,
    input Cin,
    output Cout,
    output S
    );
    assign {Cout,S} = A+B+Cin;
endmodule

`timescale 1ns / 1ps

module HA(
    input A,
    input B,
    output Cout,
    output S
    );
    assign Cout = A & B;
    assign S = A ^ B;
endmodule