Verilog tb_FullAdder.v Code
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module tb_FA(
);
reg in1,in2,in3;
wire carry,sum;
FA U1(.A(in1),.B(in2),.Cin(in3),.Cout(carry),.S(sum));
initial begin
in1=0;in2=0;in3=0; //000 -> 00
#100 in3=1; //001 -> 01
#100 in2=1; //011 -> 10
#100 in1=1; //111 -> 11
#100 in3=0; //110 -> 10
#100 in2=0; //100 -> 01
#100 $finish;
end
endmodule
test bench simulation source code file for FA.v (or FullAdder.v)
tb is short term for 'test bench'. All these test bench codes are for running simulation of design sources.
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