Verilog Vivado tb_Stopwatch.v Code
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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Testbench for stopwatch
//////////////////////////////////////////////////////////////////////////////////
module tb_stopwatch(
);
reg clk, en, rst;
wire [3:0] X0, X1, X2, X3;
wire secled;
stopwatch U0(.rst(rst), .en(en), .clk(clk), .secled(secled), .Q10(X0), .Q1(X1), .Qs1(X2), .Qs10(X3));
initial begin
clk=1'b0;
en = 1'b1;
rst = 1'b0;
#5 rst = 1'b1;
#6 rst = 1'b0;
#100 $stop;
end
always begin
#5 clk <= ~clk;
end
endmodule
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This is the Verilog code that written with Vivado for implementing Stopwatch in FPGA Board(Xilinx; Nexys S).