Verilog tb_LabAdd4bit Code
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Test for LabAdd4bit :
// A[3:0]=9; B=[3:0]=10 => Carry = 1, Sum = 3
//X0 = h84, X1 = h82, X2 = hCF, X3 = h86
//////////////////////////////////////////////////////////////////////////////////
module tb_LabAdd4bit(
);
reg [3:0] A, B;
reg clk, rst;
wire [7:0] an, seg;
LabAdd4bit U0(.A(A),.B(B),.clk(clk),.rst(rst),.AN(an),.Seg(seg));
initial begin
A=4'b1001; B=4'b1010;
clk=0; rst=1;
#23 rst=0;
end
//100MHz clock
always begin
#5 clk = !clk;
end
endmodule
test bench simulation source code file for LabAdd4bit.v
tb is short term for 'test bench'. All these test bench codes are for running simulation of design sources.
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