미래지향적person1

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: I am a college student.
// Testbench for count_8bit
//////////////////////////////////////////////////////////////////////////////////
module tb_count_8bit(

    );
    reg clk, rst, en;
    wire [7:0] count, mod_cnt, mod_02;
    wire tc01, tc02;
    
    count_8bit U0(.clk(clk), .rst(rst), .cntout(count));
    
    //Modulus 60: 0,1,2,.... 58, 59, 0, 1, 2, 3,....
    defparam U1.MOD = 10; //0,1,2,....9,0,1,2,3....
    mod_n U1 (.clk(clk), .rst(rst), .en(en), .cntout(mod_cnt), .TC(tc01));

    defparam U1.MOD = 6; //0,1,2,....5,0,1,2,3....
    mod_n U2 (.clk(clk), .rst(rst), .en(tc01), .cntout(mod_02), .TC(tc02));
        
    initial begin
        clk=1'b0;
        rst=1'b0;
        en = 1'b1;
        #1 rst=1'b1;
        #5 rst=1'b0;
        #100 $stop;
    end
    
    //100MHz clock
    always begin
        #5 clk = ~clk;
    end
    
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Stopwatch
// Input : clk, rst, enable
// Output :
// secled : on and off at every second
// Q10, Q1, Qs1, Qs10 : second subsecond output
//////////////////////////////////////////////////////////////////////////////////
module stopwatch(
    input rst,
    input en,
    input clk,
    output reg secled,
    output [3:0] Q10,
    output [3:0] Q1,
    output [3:0] Qs1,
    output [3:0] Qs10
    );
    
    wire tc01, tc02, tc03, tc04, tc05, tc06, tc07;
    wire [7:0] mcnt01, mcnt02, mcnt03;
    wire [3:0] tmp01, tmp02, tmp03, tmp04;
    
    //Modulus count 100: 10ns -> 1us
    defparam U0.MOD=100;
    mod_n U0(.rst(rst), .en(en), .clk(clk), .cntout(mcnt01), .TC(tc01));
    //1us -> 100us
    defparam U1.MOD=100;
    mod_n U1(.rst(rst), .en(tc01), .clk(clk), .cntout(mcnt02), .TC(tc02));
    
    //100us -> 10ms
    defparam U2.MOD=100;
    mod_n U2(.rst(rst), .en(en), .clk(clk), .cntout(mcnt03), .TC(tc03));
    
    defparam U3.MOD=10;
    mod_n U3(.rst(rst), .en(tc03), .clk(clk), .cntout({tmp01, Qs10}), .TC(tc04));
        
    defparam U4.MOD=10;
    mod_n U4(.rst(rst), .en(tc04), .clk(clk), .cntout({tmp02, Qs1}), .TC(tc05));
    
    always @ (posedge tc05) begin
        secled <= ~secled;
    end
    
    defparam U5.MOD=10;
    mod_n U5(.rst(rst), .en(tc05), .clk(clk), .cntout({tmp03, Q1}), .TC(tc06));
    
    defparam U6.MOD=6;
    mod_n U6(.rst(rst), .en(tc06), .clk(clk), .cntout({tmp04, Q10}), .TC(tc07));
endmodule

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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Modulus N Counter
// Input: rst, clk, en
// Output: cntout[7:0], TC
// parameter : MOD
//////////////////////////////////////////////////////////////////////////////////
module mod_n(
    input rst,
    input clk,
    input en,
    output [7:0] cntout,
    output reg TC
    );
    
    reg [7:0] cnt;
    parameter MOD = 5;
    
    always @ (posedge clk or posedge rst) begin
        if(rst==1'b1) begin
            cnt <= 8'b0000_0000;
            TC = 1'b0;
        end
        else begin
            cnt <= (en) ? cnt+1'b1 : cnt;
            TC  <= 1'b0;
            if(en & cnt == MOD-1) begin
                cnt <= 8'b0000_0000;
                TC <= 1'b1;
            end
        end
    end
    assign cntout = cnt;
endmodule