미래지향적person1

# A, B
set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { A }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { B }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]

# Cout, Sum
set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { S }]; #IO_L18P_T2_A24_15 Sch=led[0]
set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { Cout }]; #IO_L24P_T3_RS1_15 Sch=led[1]

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////////////////
module FA(
    input A,
    input B,
    input Cin,
    output Cout,
    output S
    );
    assign {Cout,S} = A+B+Cin;
endmodule

`timescale 1ns / 1ps

module HA(
    input A,
    input B,
    output Cout,
    output S
    );
    assign Cout = A & B;
    assign S = A ^ B;
endmodule

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Lab 4bit adder : 

// A[3:0],B[3:0],clk,rst --> AN[7:0], Seg[7:0]

//////////////////////////////////////////////////////////////////////////////////

module LabAdd4bit(
    input [3:0] A,
    input [3:0] B,
    input clk,
    input rst,
    output [7:0] AN,
    output [7:0] Seg
    );
    
    wire [3:0] carry, sum;
    assign carry[3:1] = 3'b000;

    Add4bit U1(.A(A), .B(B), .Cout(carry[0]), .S(sum));
    Dsp7Seg U2(.X0(A), .X1(B), .X2(carry), .X3(sum), .clk(clk), .rst(rst), .AN(AN),.dsp(Seg));
endmodule