Verilog Add 4 Bit Code
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
module Add4bit(
input [3:0] A,
input [3:0] B,
output Cout,
output [3:0] S
);
wire [2:0] tmp;
HA U0(.A(A[0]),.B(B[0]),.Cout(tmp[0]),.S(S[0]));
FA U1(.A(A[1]),.B(B[1]),.Cin(tmp[0]),.Cout(tmp[1]),.S(S[1]));
FA U2(.A(A[2]),.B(B[2]),.Cin(tmp[1]),.Cout(tmp[2]),.S(S[2]));
FA U3(.A(A[3]),.B(B[3]),.Cin(tmp[2]),.Cout(Cout),.S(S[3]));
endmodule
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