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`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: I am a college student.
// Testbench for count_8bit
//////////////////////////////////////////////////////////////////////////////////
module tb_count_8bit(
);
reg clk, rst, en;
wire [7:0] count, mod_cnt, mod_02;
wire tc01, tc02;
count_8bit U0(.clk(clk), .rst(rst), .cntout(count));
//Modulus 60: 0,1,2,.... 58, 59, 0, 1, 2, 3,....
defparam U1.MOD = 10; //0,1,2,....9,0,1,2,3....
mod_n U1 (.clk(clk), .rst(rst), .en(en), .cntout(mod_cnt), .TC(tc01));
defparam U1.MOD = 6; //0,1,2,....5,0,1,2,3....
mod_n U2 (.clk(clk), .rst(rst), .en(tc01), .cntout(mod_02), .TC(tc02));
initial begin
clk=1'b0;
rst=1'b0;
en = 1'b1;
#1 rst=1'b1;
#5 rst=1'b0;
#100 $stop;
end
//100MHz clock
always begin
#5 clk = ~clk;
end
endmodule
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