Verilog Half Adder Constraints File

Verilog Half Adder Constraints File

# A, B
set_property -dict { PACKAGE_PIN J15   IOSTANDARD LVCMOS33 } [get_ports { A }]; #IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN L16   IOSTANDARD LVCMOS33 } [get_ports { B }]; #IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]

# Cout, Sum
set_property -dict { PACKAGE_PIN H17   IOSTANDARD LVCMOS33 } [get_ports { S }]; #IO_L18P_T2_A24_15 Sch=led[0]
set_property -dict { PACKAGE_PIN K15   IOSTANDARD LVCMOS33 } [get_ports { Cout }]; #IO_L24P_T3_RS1_15 Sch=led[1]

ha_xdc.xdc  , Half Adder Constraints

xdc: Xilinx's Design Constraints File