Verilog Lab_4_Bit_Adder Code

`timescale 1ns / 1ps

//////////////////////////////////////////////////////////////////////////////////

// Lab 4bit adder : 

// A[3:0],B[3:0],clk,rst --> AN[7:0], Seg[7:0]

//////////////////////////////////////////////////////////////////////////////////

module LabAdd4bit(
    input [3:0] A,
    input [3:0] B,
    input clk,
    input rst,
    output [7:0] AN,
    output [7:0] Seg
    );
    
    wire [3:0] carry, sum;
    assign carry[3:1] = 3'b000;

    Add4bit U1(.A(A), .B(B), .Cout(carry[0]), .S(sum));
    Dsp7Seg U2(.X0(A), .X1(B), .X2(carry), .X3(sum), .clk(clk), .rst(rst), .AN(AN),.dsp(Seg));
endmodule

Verilog Lab_4_Bit_Adder Code